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active receive mixer lf to 3 ghz ad8342 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007C2009 analog devices, inc. all rights reserved. features broadband rf, lo, and if ports conversion gain: 3.7 db noise figure: 12.2 db input ip3: 22.7 dbm input p1db: 8.3 dbm lo drive: 0 dbm differential high impedance rf input port single-ended, 50 lo input port open-collector if output port single-supply operation: 5 v @ 98 ma power-down mode exposed paddle lfcsp: 3 mm 3 mm applications cellular base station receivers ism receivers radio links rf instrumentation functional block diagram 8 7 6 13 15 16 comm ifop ifom 5 comm 14 2 1 3 4 comm rfcm rfin vpmx v pdc pwdn exrb comm 11 12 10 9 vplo locm loin comm bias ad8342 05352-001 figure 1. general description the ad8342 is a high performance, broadband active mixer. it is well suited for demanding receive-channel applications that require wide bandwidth on all ports and very low intermodulation distortion and noise figure. the ad8342 provides a typical conversion gain of 3.7 db with an rf frequency of 238 mhz. the integrated lo driver presents a 50 input impedance with a low lo drive level, helping to minimize the external component count. the differential high impedance broadband rf port allows for easy interfacing to both active devices and passive filters. the rf input accepts input signals as large as 1.6 v p-p or 8 dbm (relative to 50 ) at p1db. the open-collector differential outputs provide excellent balance and can be used with a differential filter or if amplifier, such as the ad8370, ad8375, ad8351 , ad8352 , or adl5561 . these outputs can also be converted to a single-ended signal using a matching network or a balun transformer. the outputs are capable of swinging 2 v p-p when biased to the vpos supply rail. the ad8342 is fabricated on an analog devices, inc., proprietary, high performance sige ic process. the ad8342 is available in a 16-lead lfcsp. it operates over a ?40c to +85c temperature range. an evaluation board is also available.
ad8342 rev. b | page 2 of 24 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 ac performance ........................................................................... 4 spur table .......................................................................................... 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ..............................................8 circuit description......................................................................... 14 ac interfaces ................................................................................... 15 if port .......................................................................................... 16 lo considerations ..................................................................... 17 high frequency applications ................................................... 18 low frequency applications .................................................... 19 evaluation board ............................................................................ 21 outline dimensions ....................................................................... 24 ordering guide .......................................................................... 24 revision history 7/09rev. a to rev. b ch anged rf and lo frequency range from 2.4 ghz to 3 ghz throughout ........................................................................... 1 changes to general description section ...................................... 1 added endnote 2 .............................................................................. 4 added low frequency applications section .............................. 19 added figure 56 and figure 57..................................................... 20 changes to the evaluation board section ................................... 21 added figure 59 to figure 62 ........................................................ 22 updated outline dimensions ....................................................... 24 changes to ordering guide .......................................................... 24 1/07rev. 0 to rev. a changes to features .......................................................................... 1 changes to general description .................................................... 1 changes to table 2 ............................................................................ 4 replaced the high frequency applications section .................. 18 4/05revision 0: initial version
ad8342 rev. b | page 3 of 24 specifications v s = 5 v, t a = 25c, f rf = 238 mhz, f lo = 286 mhz, lo power = 0 dbm, z o = 50 , r bias = 1.82 k, rf termination = 100 , if terminated into 100 through a 2:1 ratio balun, unless otherwise noted. table 1. parameter conditions min typ max unit rf input interface return loss high-z input terminated wi th 100 off-chip resistor 10 db input impedance frequency = 238 mhz (measured at rfin with rfcm ac-grounded) 1||0.4 k||pf dc bias level internally generated; port must be ac-coupled 2.4 v output interface output impedance differential impedance, frequency = 48 mhz 10||0.5 k||pf dc bias voltage supplied externally 4.75 v s 5.25 v power range via a 2:1 impedance ratio transformer 13 dbm lo interface return loss 10 db dc bias voltage internally genera ted; port must be ac-coupled v s ? 1.6 v power-down interface pwdn threshold 3.5 v pwdn response time device enabled, if output to 90% of its final level 0.4 s device disabled, supply current <5 ma 4 s pwdn input bias current device enabled ?80 a device disabled +100 a power supply positive supply voltage 4.75 5 5.25 v quiescent current vpdc supply current for bias cells 5 ma vpmx, ifop, ifom supply current for mixer, r bias = 1.82 k 58 ma vplo supply current for lo limiting amplifier 35 ma total quiescent current v s = 5 v 85 98 113 ma power-down current device disabled 500 a
ad8342 rev. b | page 4 of 24 ac performance v s = 5 v, t a = 25c, lo power = 0 dbm, z o = 50 , r bias = 1.82 k, rf termination 100 , if terminated into 100 via a 2:1 ratio balun, unless otherwise noted. table 2. parameter conditions min typ max unit rf frequency range 1 3.0 ghz lo frequency range 1 3.0 ghz if frequency range 1 , 2 2.4 ghz conversion gain f rf = 460 mhz, f lo = 550 mhz, f if = 90 mhz 3.2 db f rf = 238 mhz, f lo = 286 mhz, f if = 48 mhz 3.7 db ssb noise figure f rf = 460 mhz, f lo = 550 mhz, f if = 90 mhz 12.5 db f rf = 238 mhz, f lo = 286 mhz, f if = 48 mhz 12.2 db input third-order intercept f rf1 = 460 mhz, f rf2 = 461 mhz, f lo = 550 mhz, f if1 = 90 mhz, f if2 = 89 mhz, each rf tone ?10 dbm 22.2 dbm f rf1 = 238 mhz, f rf2 = 239 mhz, f lo = 286 mhz, f if1 = 48 mhz, f if2 = 47 mhz, each rf tone ?10 dbm 22.7 dbm input second-order intercept f rf1 = 460 mhz, f rf2 = 410 mhz, f lo = 550 mhz, f if1 = 90 mhz, f if2 = 140 mhz 50 dbm f rf1 = 238 mhz, f rf2 = 188 mhz, f lo = 286 mhz, f if1 = 48 mhz, f if2 = 98 mhz 44 dbm input 1 db compression point f rf = 460 mhz, f lo = 550 mhz, f if = 90 mhz 8.5 dbm f rf = 238 mhz, f lo = 286 mhz, f if = 48 mhz 8.3 dbm lo to if output leakage lo power = 0 dbm, f lo = 286 mhz ?27 dbc lo to rf input leakage lo power = 0 dbm, f lo = 286 mhz ?55 dbc 2 lo to if output leakage lo power = 0 dbm, f rf = 238 mhz, f lo = 286 mhz if terminated into 100 and measured with a differential probe ?47 dbm rf to if output leakage rf power = ?10 dbm, f rf = 238 mhz, f lo = 286 mhz ?32 dbc if/2 spurious rf power = ?10 dbm, f rf = 238 mhz, f lo = 286 mhz ?62 dbc 1 see the section for details. high frequency applications 2 see the low frequency applications section for details.
ad8342 rev. b | page 5 of 24 spur table v s = 5 v, t a = 25c, rf and lo power = 0 dbm, f rf = 238 mhz, f lo = 286mhz, z o = 50 , r bias = 1.82 k, rf termination 100 , if terminated into 100 via a 2:1 ratio balun. note: measured using standard test board. typical noise floor of measurement system = ?100 dbm. table 3. m n nf rf ? mf lo 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0 ad8342 rev. b | page 6 of 24 absolute maximum ratings stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 4. parameter rating supply voltage, v s 5.5 v rf input level 12 dbm lo input level 12 dbm pwdn pin v s + 0.5 v ifop, ifom bias voltage 5.5 v minimum resistor from exrb to comm 1.8 k internal power dissipation 650 mw ja 77c/w maximum junction temperature 135c operating temperature range ?40c to +85c storage temperature range ?65c to +150c esd caution
ad8342 rev. b | page 7 of 24 pin configuration and fu nction descriptions 0 5352-002 pin 1 indicator 1 vplo 2 locm 3 loin 4 comm 11 pwdn 12 vpdc 10 exrb 9comm 5 c omm 6 ifom 7 ifop 8 comm 15 rfin 16 vpmx 14 rfc m 13 comm top view (not to scale) ad8342 figure 2. 16-lead lfcsp table 5. pin function descriptions pin no. mnemonic description 1 vplo positive supply voltage for the lo buffer: 4.75 v to 5.25 v. 2 locm ac ground for limiting lo amplifier. internally biased to v s ? 1.6 v. ac-couple to ground. 3 loin lo input. nominal input level: 0 dbm. input level rang e: ?10 dbm to +4 dbm (relative to 50 ). internally biased to v s ? 1.6 v. must be ac-coupled. 4, 5, 8, 9, 13 comm device common (dc ground). 6, 7 ifom, ifop differential if outputs (open colle ctors). each requires dc bias of 5.00 v (nominal). 10 exrb mixer bias voltage. connect resistor from exrb to gr ound. typical value of 1.82 k sets mixer current to nominal value. minimum resistor value from exrb to ground = 1.8 k. internally biased to 1.17 v. 11 pwdn connect to ground for normal operation. connect pin to v s for disable mode. 12 vpdc positive supply voltage for the dc bias cell: 4.75 v to 5.25 v. 14 rfcm ac ground for rf input. internally biased to 2.4 v. ac-couple to ground. 15 rfin rf input. internally biased to 2.4 v. must be ac-coupled. 16 vpmx positive supply voltage for the mixer: 4.75 v to 5.25 v.
ad8342 rev. b | page 8 of 24 typical performance characteristics v s = 5 v, t a = 25c, rf power = ?10 dbm, lo power = 0 dbm, z o = 50 , r bias = 1.82 k, rf termination 100 , if terminated into 100 via a 2:1 ratio balun, unless otherwise noted. 05352-004 rf frequency (mhz) gain (db) if = 10mhz 50 550 100 150 200 250 300 350 400 450 500 if = 90mhz 6 5 4 3 2 1 if = 48mhz if = 140mhz figure 3. conversion gain vs. rf frequency 5 0 05352-025 lo level (dbm) gain (db) ?15 ?10 ?5 0 5 if = 48mhz if = 90mhz if = 140mhz 4 3 2 1 if = 10mhz figure 4. gain vs. lo level, rf frequency = 238 mhz 5.0 0 05352-039 temperature (c) gain (db) 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 ?200 20406080 ?40 figure 5. gain vs. temperature, f rf = 238 mhz, f lo = 286 mhz 5 1 05352-005 if frequency (mhz) gain (db) 6 4 3 2 5010 100 150 200 250 300 350 rf = 238mhz rf = 460mhz figure 6. conversion gain vs. if frequency 5.0 0 05352-026 vpos (v) gain (db) 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 4.75 5.25 4.85 4.95 5.05 5.15 figure 7. gain vs. vpos, f rf = 238 mhz, f lo = 286 mhz 50 0 3.40 3.90 05352-054 conversion gain (238mhz) percentage 45 40 35 30 25 20 15 10 5 3.45 3.50 3.55 3.60 3.65 3.70 3.75 3.80 3.85 normal mean = 3.7 std. dev. = 0.06 figure 8. conversion gain distribution, f rf = 238 mhz, f lo = 286 mhz
ad8342 rev. b | page 9 of 24 27 17 50 550 05352-007 rf frequency (mhz) input ip3 (dbm) 100 150 200 250 300 350 400 450 500 26 25 24 23 22 21 20 19 18 if = 10mhz if = 140mhz if = 90mhz if = 48mhz figure 9. input ip3 vs. rf frequency 27 17 ?15 5 05352-027 lo level (dbm) input ip3 (dbm) 26 25 24 23 22 21 20 19 18 ?13?11?9?7?5?3?1 1 3 if = 10mhz if = 48mhz if = 90mhz 140mhz figure 10. input ip3 vs. lo level, f rf1 = 238 mhz, f rf2 = 239 mhz 27 17 05352-032 temperature (c) input ip3 (dbm) ?200 20406080 ?40 26 25 24 23 22 21 20 19 18 figure 11. input ip3 vs. temperature, f rf1 = 238 mhz, f rf2 = 239 mhz, f lo = 286 mhz 27 17 10 05352-008 if frequency (mhz) input ip3 (dbm) 350 26 25 24 23 22 21 20 19 18 50 100 150 200 250 300 rf = 460mhz rf = 238mhz figure 12. input ip3 vs. if frequency 05352-028 vpos (v) input ip3 (dbm) 27 17 4.75 5.25 26 25 24 23 22 21 20 19 18 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 figure 13. input ip3 vs. vpos, f rf = 238 mhz, f rf2 = 239 mhz lo frequency = 286 mhz 20 0 20.6 05352-055 input ip3 (238mhz) percentage 18 16 14 12 10 8 6 4 2 21.0 21.4 21.8 22.2 22.6 23.0 23.4 23.8 24.2 normal mean = 22.7 std. dev. = 0.41 figure 14. input ip 3 distribution, f rf = 238 mhz, f lo = 286 mhz
ad8342 rev. b | page 10 of 24 13 3 50 550 05352-013 rf frequency (mhz) input p1db (dbm) 12 11 10 9 8 7 6 5 4 100 150 200 250 300 350 400 450 500 10mhz 140mhz 48mhz 90mhz figure 15. input p1db vs. rf frequency 10.0 5.0 ?15 5 05352-038 lo level (dbm) input p1db (dbm) 9.5 9.0 8.5 8.0 7.5 7.0 6.5 6.0 5.5 ?13?11?9?7?5?3?1 1 3 if = 10mhz if = 48mhz if = 90mhz if = 140mhz figure 16. input p1db vs. lo level, f rf = 238 mhz 10 0 05352-033 temperature (c) input p1db (dbm) 9 8 7 6 5 4 3 2 1 ?200 20406080 ?40 figure 17. input p1db vs. temperature, f rf = 238 mhz, f lo = 286 mhz 10 0 10 05352-014 if frequency (mhz) input p1db (dbm) 9 8 7 6 5 4 3 2 1 50 100 150 200 250 300 350 rf = 460mhz rf = 238mhz figure 18. input p1db vs. if frequency 05352-031 input p1db (dbm) 10 0 9 8 7 6 5 4 3 2 1 vpos (v) 4.75 5.25 4.85 4.95 5.05 5.15 figure 19. input p1db vs. vpos, f rf = 238 mhz, f lo = 286 mhz 28 0 8.00 05352-056 ip1db (238mhz) percentage 8.60 26 24 22 20 18 16 14 12 10 8 6 4 2 8.05 8.10 8.15 8.20 8.25 8.30 8.35 8.40 8.45 8.50 8.55 normal mean = 8.3 std. dev. = 0.07 figure 20. input ip 3 distribution, f rf = 238 mhz, f lo = 286 mhz
ad8342 rev. b | page 11 of 24 60 0 100 550 05352-010 rf frequency (mhz) input ip2 (dbm) 50 40 30 20 10 if = 10mhz if = 140mhz if = 90mhz if = 48mhz 150 200 250 300 350 400 450 500 figure 21. input ip2 vs. rf frequency (second rf = rf ? 50 mhz) 60 40 05352-029 input ip2 (dbm) 58 56 54 52 50 48 46 44 42 ?15 5 lo level (dbm) ?13 ?11 ?9 ?7 ?5 ?3 ?1 1 3 if = 10mhz if = 48mhz if = 90mhz if = 140mhz figure 22. input ip2 vs. lo level, f rf = 238 mhz, f rf2 = 188 mhz 14.0 11.0 50 550 05352-016 rf frequency (mhz) noise figure (db) 13.5 13.0 12.5 12.0 11.5 100 150 200 250 300 350 400 450 500 figure 23. noise figure vs. rf frequency, if frequency = 48 mhz 60 0 10 05352-011 if frequency (mhz) input ip2 (dbm) 50 40 30 20 10 50 100 150 200 250 300 350 rf = 238mhz rf = 460mhz figure 24. input ip2 vs. if frequency (second rf = rf ? 50 mhz) 05352-030 input ip2 (dbm) 60 40 58 56 54 52 50 48 46 44 42 vpos (v) 4.75 5.25 4.85 4.95 5.05 5.15 figure 25. input ip2 vs. vpos, f rf1 = 238 mhz, f rf2 = 188 mhz, f lo = 286 mhz 16 0 10 05352-017 if frequency (mhz) noise figure (db) 14 12 10 8 6 4 2 60 110 160 210 260 310 rf = 460mhz rf = 238mhz figure 26. noise figu re vs. if frequency
ad8342 rev. b | page 12 of 24 16 10 ?15 5 05352-018 lo power (dbm) nf (db) 15 14 13 12 11 ?13?11?9?7?5?3?1 1 3 nf = 10mhz nf = 48mhz nf = 90mhz nf = 140mhz figure 27. noise figure vs. lo power, f rf = 238 mhz 5.0 0 1.8 05352-024 r bias (k ? ) gain (db) 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 figure 28. gain vs. r bias , rf frequency = 238 mhz, lo frequency = 286 mhz 61 45 1.8 05352-037 r bias (k ? ) input ip2 (dbm) 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 59 57 55 53 51 49 47 figure 29. input ip2 vs. r bias , f rf = 238 mhz (second rf = rf C 50 mhz), f lo = 286 mhz 30 0 11.8 12.8 05352-023 noise figure (db) percentage 25 20 15 10 5 11.9 12.0 12.1 12.2 12.3 12.4 12.5 12.6 12.7 normal mean = 12.25 std. dev. = 0.14 figure 30. noise figure distribution, f rf = 238 mhz, f lo = 286 mhz 30 0 1.8 3.0 05352-015 r bias (k ? ) noise figure and input ip3 (dbm) 25 20 15 10 5 2.0 2.2 2.4 2.6 2.8 105 75 100 95 90 85 80 supply current (ma) input ip3 noise figure current figure 31. noise figure, input ip3, and supply current vs. r bias , f rf1 = 238 mhz, f rf2 = 239 mhz, f lo = 286 mhz 10 0 1.8 05352-036 r bias (k ? ) input p1db (dbm) 9 8 7 6 5 4 3 2 1 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 figure 32. input p1db vs. r bias , f rf = 238 mhz, f lo = 286 mhz
ad8342 rev. b | page 13 of 24 0 ?90 50 05352-021 lo frequency (mhz) leakage (dbc) ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 250 450 650 850 figure 33. lo to rf leakage vs. lo frequency, lo power = 0 dbm 0 ?45 50 550 05352-035 rf frequency (mhz) feedthrough (dbc) ?5 ?10 ?15 ?20 ?25 ?30 ?35 ?40 100 150 200 250 300 350 400 450 500 if = 10mhz if = 48mhz figure 34. rf to if feedthrough, rf power = ?10 dbm 0 ?45 50 850 05352-020 lo frequency (mhz) feedthrough (dbc) ?5 ?10 ?15 ?20 ?25 ?30 ?35 ?40 150 250 350 450 550 650 750 figure 35. lo to if feedthrough vs. lo frequency, lo power = 0 dbm 120 0 05352-034 temperature (c) supply current (ma) ?200 20406080 ?40 100 80 60 40 20 figure 36. supply current vs. temperature 0 ?18 60 860 05352-059 lo frequency (mhz) return loss (db) ?2 ?4 ?6 ?8 ?10 ?12 ?14 ?16 160 260 360 460 560 660 760 figure 37. lo return loss vs. lo frequency 8 7 6 13 15 16 comm ifop ifom 5 comm 14 2 1 3 4 comm rfcm rfin vpmx vpdc pwdn exrb comm 11 12 10 9 vplo locm loin comm ad8342 rf in 1nf 100pf 0.1f 100pf 0.1f v pos 1nf 1nf lo in tc2-1t if out (50 ? ) 100pf 0.1f vpos 1nf 100 ? 1.82k ? 100pf vpos 100pf 0.1f 05352-058 figure 38. characterization circuit used to measure typical performance characteristics data
ad8342 rev. b | page 14 of 24 circuit description the ad8342 is an active mixer, optimized for operation within the input frequency range of near dc to 2.4 ghz. it has a differential, high impedance rf input that can be terminated or matched externally. the rf input can be driven either single- ended or differentially. the lo input is a single-ended 50 input. the if outputs are differential open-collectors. the mixer current can be adjusted by the value of an external resistor to optimize performance for gain, compression, and intermodula- tion, or for low power operation. figure 39 shows the basic blocks of the mixer, including the lo buffer, rf voltage-to- current converter, bias cell, and mixing core. the rf voltage to rf current conversion is done via a resistively degenerated differential pair. to drive this port single-ended, the rfcm pin should be ac-grounded while the rfin pin is ac- coupled to the signal source. the rf inputs can also be driven differentially. the voltage-to-current converter then drives the emitters of a four-transistor switching core. this switching core is driven by an amplified version of the local oscillator signal connected to the lo input. there are three limiting gain stages between the external lo signal and the switching core. the first stage converts the single-ended lo drive to a well-balanced differential drive. the differential drive then passes through two more gain stages, which ensures that a limited signal drives the switching core. this affords the user a lower lo drive requirement, while maintaining excellent distortion and compression performance. the output signal of these three lo gain stages drives the four transistors within the mixer core to commutate at the rate of the local oscillator frequency. the output of the mixer core is taken directly from its open collectors. the open-collector outputs present a high impedance at the if frequency. the conversion gain of the mixer depends directly on the impedance presented to these open collectors. in characterization, a 100 load was presented to the part via a 2:1 impedance transformer. the device also features a power-down function. application of a logic low at the pwdn pin allows normal operation. a high logic level at the pwdn pin shuts down the ad8342. power consumption when the part is disabled is less than 10 mw. the bias for the mixer is set with an external resistor (r bias ) from the exrb pin to ground. the value of this resistor directly affects the dynamic range of the mixer. the external resistor should not be lower than 1.82 k. permanent damage to the part can result if values below 1.8 k are used. this resistor sets the dc current through the mixer core. the performance effects of changing this resistor can be seen in the typical performance characteristics section. 0 5352-040 lo input vplo ifop ifom rfin rfcm bias extern a l bias resistor vpdc pwdn v to i figure 39. simplified schematic showing the key elements of the ad8342 as shown in figure 40 , the if output pins, ifop and ifom, are directly connected to the open collectors of the npn transistors in the mixer core so the differential and single-ended impedances looking into this port are relatively high, on the order of several k. a connection between the supply voltage and these output pins is required for proper mixer core operation. 05352-041 ifop ifom loin rfcm rfin comm figure 40. ad8342 simplified schematic the ad8342 has three pins for the supply voltage: vpdc, vpmx, and vplo. these pins are separated to minimize or eliminate possible parasitic coupling paths within the ad8342 that could cause spurious signals or reduced interport isolation. consequently, each of these pins should be well bypassed and decoupled as close to the ad8342 as possible.
ad8342 rev. b | page 15 of 24 ac interfaces the ad8342 is designed to downconvert radio frequencies (rf) to lower intermediate frequencies (if) using a high- or low-side local oscillator (lo). the lo is injected into the mixer core at a frequency higher or lower than the desired input rf. the frequency difference between the lo and the rf, f lo ? f rf (high side) or f rf ? f lo (low side), is the intermediate frequency, f if . in addition to the desired rf signal, an rf image is downconverted to the desired if frequency. the image frequency is at f lo + f if when driven with a high-side lo. when using a broadband load, the conversion gain of the ad8342 is nearly constant over the specified rf input band (see figure 3 ). the ad8342 is designed to operate over a broad frequency range. it is essential to ac couple rf and lo ports to prevent dc offsets from skewing the mixer core in an asymmetrical manner, potentially degrading noise figure and linearity. the rf input of the ad8342 is high impedance, 1 k across the frequency range shown in figure 41 . the input capacitance decreases with frequency due to package parasitics. 2.00 1.00 00 0 1g 05352-042 frequency (hz) resistance (k ? ) capacitance (pf) 1.75 1.50 0.75 1.25 1.00 0.50 0.75 0.50 0.25 0.25 100m 200m 300m 400m 500m 600m 700m 800m 900m figure 41. rf input impedance the matching or termination used at the rf input of the ad8342 has a direct effect on its dynamic range. the characterization circuit, as well as the evaluation board, uses a 100 resistor to terminate the rf port. this termination resistor in shunt with the input stage results in a return loss of better than ?10 dbm (relative to 50 ). table 6 shows gain, ip3, p1db, and noise figure for four different input networks. this data was measured at an rf frequency of 250 mhz and at an lo frequency of 300 mhz. table 6. dynamic performance for various input networks input network 50 shunt 100 shunt 500 shunt matched ( figure 42 ) gain (db) 0.66 3.5 5.3 9.3 iip3 (dbm) 25.4 22.9 20. 6 18.5 p1db (dbm) 10.8 8.4 6.3 2.3 nf (db) 14 12.5 10.2 10.5 the rf port can also be matched using an lc circuit, as shown in figure 42 . 0 5352-043 z l 1k? z o = 50 ? f main = 250mhz 50? 3.6pf 100nh (1000 + j0) ? figure 42. matching circuit impedance transformations of greater than 10:1 result in a higher q circuit and thus a narrow rf input bandwidth. a 1 k resistor is placed across the rf input of the device in parallel with the device internal input impedance, creating a 500 load. this impedance is matched to as close as possible to 50 for the source, with standard components using a shunt c, series l matching circuit (see figure 43 ). 05352-044 25 10 10 25 50 100 200 500 500 200 100 50 q = 3 1 2 3 4 point 1(1000 + j0) ? point 2(500 + j0) ? point 3(55.6 ? j157.2) ? point 4(55.6 ? j0.1) ? figure 43. lc matching example
ad8342 rev. b | page 16 of 24 if port the if port comprises open-collector differential outputs. the npn open collectors can be modeled as current sources that are shunted with resistances of ~10 k in parallel with capacitances of ~1 pf. the specified performance numbers for the ad8342 were measured with 100 differential terminations. however, different load impedances can be used where circumstances dictate. in general, lower load impedances result in lower conversion gain and lower output p1db. higher load imped- ances result in higher conversion gain for small signals, but lower ip3 values for both input and output. if the if signal is to be delivered to a remote load, more than a few millimeters away at high output frequencies, avoid unintended parasitic effects due to the intervening pcb traces. one approach is to use an impedance transforming network or transformer located close to the ad8342. if very wideband output is desired, a nearby buffer amplifier may be a better choice, especially if if response to dc is required. an example of such a circuit is presented in figure 45 , in which the ad8351 differential amplifier is used to drive a pair of 75 transmission lines. the gain of the buffer can be independently set by appropriate choice of the value for the gain resistor, r g . 50 0.5 0 0 1g 05352-045 frequency (hz) resistance (k ? ) capacitance (pf) 45 0.4 40 0.3 35 0.2 30 0.1 25 0 20 ?0.1 15 ?0.2 10 5 100m 200m 300m 400m 500m 600m 700m 800m 900m figure 44. if port impedance 05352-046 comm 8 ifop 7 ifom 6 comm 5 ad8342 ad8351 + ? r fc +v s rfc z l = 100 ? +v s +v s 100 ? r g z l tx line z o = 75 ? tx line z o = 75 ? figure 45. ad8351 used as transmission line driver and impedance buffer the high input impedance of the ad8351 allows for a shunt differential termination to provide the desired 100 load to the ad8342 if output port. it is necessary to bias the open-collector outputs using one of the schemes presented in figure 47 and figure 48 . figure 47 illustrates the application of a center-tapped impedance transformer. the turns ratio of the transformer should be selected to provide the desired impedance transformation. in the case of a 50 load impedance, a 2-to-1 impedance ratio transformer should be used to transform the 50 load into a 100 differential load at the if output pins. figure 48 illustrates a differential if interface where pull-up choke inductors are used to bias the open-collector outputs. the shunting impedance of the choke inductors used to couple dc current into the mixer core should be large enough at the if operating frequency so it does not load down the output current before reaching the intended load. additionally, the dc current handling capability of the selected choke inductors needs to be at least 45 ma. the self-resonant frequency of the selected choke should be higher than the intended if frequency. a variety of suitable choke inductors is commercially available from manufacturers such as murata and coilcraft?. figure 46 shows the loading effects when using nonideal inductors. an impedance transforming network may be required to transform the final load impedance to 100 at the if outputs. there are several good reference books that explain general impedance matching procedures, including: ? chris bowick, rf circuit design , newnes, reprint edition, 1997. ? david m. pozar, microwave engineering , wiley, 3rd edition, 2004. ? guillermo gonzalez, microwave transistor amplifiers: analysis and design , prentice hall, second edition, 1996. 05352-049 0 180 30 330 50mhz 50mhz 500mhz 500mhz 60 90 270 300 120 240 150 210 real chokes ideal chokes figure 46. if port loading effects due to finite q pull-up inductors (murata blm18hd601sn1d chokes)
ad8342 rev. b | page 17 of 24 05352-047 comm 8 ifop 7 ifom 6 comm 5 ad8342 z l = 100 ? if out z o = 50 ? +v s 2:1 figure 47. biasing the if port open-collector outputs using a center-tapped impedance transformer 05352-048 comm 8 ifop 7 ifom 6 comm 5 ad8342 rfc +v s rfc z l = 100 ? if out+ if out? +v s z l impedance transforming network figure 48. biasing the if port open-collector outputs using pull-up choke inductors the ad8342 is optimized for driving a 100 load. although the device is capable of driving a wide variety of loads, to maintain optimum distortion and noise performance, it is advised that the presented load at the if outputs is close to 100 . the linear differential vo ltage conversion gain of the mixer can be modeled as load m v rga = where: em m m rg g g + = 1 1 r load is the single-ended load impedance. g m is the transistor transconductance and is equal to 1810/r bias . r e = 15 . the external r bias resistor is used to control the power dissipation and dynamic range of the ad8342. because the ad8342 has internal resistive dege neration, the conversion gain is primarily determined by the load impedance and the on-chip degeneration resistors. figure 49 shows how gain varies with if load. the external r bias resistor has only a small effect. the most direct way to affect conversion gain is by varying the load impedance. small loads result in lower gains while larger loads increase the conversion gain. if the if load impedance is too large, it causes a decrease in linearity (p1db, ip3). in order to maintain positive conversion gain and preserve sfdr performance, the differential load presented at the if port should remain in the range of about 100 to 250 . 30 0 10 1000 05352-057 if load ( ? ) voltage gain (db) 100 25 20 15 10 5 measured modeled figure 49. voltage conversion gain vs. if loading lo considerations the loin port provides a 50 load impedance with common- mode decoupling on locm. again, common-grade ceramic capacitors provide sufficient signal coupling and bypassing of the lo interface. the lo signal needs to have adequate phase noise characteristics and low second-harmonic content to prevent degradation of the noise figure performance of the ad8342. an lo plagued with poor phase noise can result in reciprocal mixing, a mechanism that causes spectral spreading of the downconverted signal, limiting the sensitivity of the mixer at frequencies adjacent to any large input signals. the internal lo buffer provides enough gain to hard-limit the input lo and provide fast switching of the mixer core. odd harmonic content present on the lo drive signal should not impact mixer performance; however, even- order harmonics cause the mixer core to commutate in an unbalanced manner, potentially degrading noise performance. simple lumped element low-pass filtering can be applied to help reject the harmonic content of a given local oscillator, as shown in figure 50 . the filter depicted is a common 3-pole chebyshev, designed to maintain a 1-to-1 source-to-load impedance ratio with no more than 0.5 db of ripple in the pass band. other filter structures can be effective as long as the second harmonic of the lo is filtered to negligible levels, for example, ~30 db below the fundamental. 05352-050 ad8342 loin 3 comm 4 locm 2 r l for r s = r l f c - filter cutoff frequency r s c1 c3 lo source l2 c1 = 1.864 2 f c r l c3 = 1.834 2 f c r l l2 = 1.28r l 2 f c figure 50. using a low-pass filter to reduce lo second harmonic
ad8342 rev. b | page 18 of 24 high frequency applications the ad8342 is a broadband mixer capable of both up and down conversion. unlike other mixers that rely on on-chip reactive circuitry to optimize performance over a specific band, the ad8342 is a versatile general-purpose device that can be used from arbitrarily low frequencies to several ghz. in general, the following considerations help to ensure optimum performance: ? minimize ac loading impedance of if port bias network. ? maximize power transfer to the desired ac load. ? for maximum conversion gain and the lowest noise performance, reactively match the input as described in the if port section. ? for maximum input compression point and input intercept points, resistively terminate the input as described in the if port section. as an example, figure 51 shows the ad8342 as an up- converting mixer for a w-cdma single-carrier transmitter design. for this application, it was desirable to achieve ?65 dbc adjacent channel power ratio (acpr) at a ?13 dbm output power level. the acpr is a measure of both distortion and noise carried into an adjacent frequency channel due to the finite intercept points and noise figure of an active device. 8 7 6 13 15 16 comm ifop ifom 5 comm 14 2 1 3 4 comm rfcm rfin vpmx vpdc pwdn exrb comm 11 12 10 9 vplo locm loin comm ad8342 05352-052 vpos vpos 34nh 34nh 100pf 100pf 1nf 1nf etc1-1-13 100pf 100pf 0.1f vpos 1nf 1nf 1970mhz osc 1.82k ? 100pf 4.7pf 170mhz input 100nh 1nf 499 ? vpos 100pf 0.1pf 2140mhz out 1nf figure 51. w-cdma tx up-con version application circuit because a w-cdma channel encompasses a bandwidth of almost 5 mhz, it is necessary to keep the q of the matching circuit low enough so that phase and magnitude variations are below an acceptable level over the 5 mhz band. it is possible to use purely reactive matching to transform a 50 source to match the raw ~1 k input impedance of the ad8342. however, the l and c component variations could present production concerns due to the sensitivity of the match. for this application, it is advantageous to shunt down the ~1 k input impedance using an external shunt termination resistor to allow for a lower q reactive matching network. the input is terminated across the rfin and rfcm pins using a 499 termination. the termination should be as close to the device as possible to minimize standing wave concerns. the rfcm is bypassed to ground using a 1 nf capacitor. a dc blocking capacitor of 1 nf is used to isolate the dc input voltage present on the rfin pin from the source. a step-up impedance transformation is realized using a series l shunt c reactive network. the actual values used need to accommodate for the series l and stray c parasitics of the connecting transmission line segments. when using the customer evaluation board with the components specified in figure 51 , the return loss over a 5 mhz band centered at 170 mhz was better than 10 db. external pull-up choke inductors are used to feed dc bias into the open-collector outputs. it is desirable to select pull-up choke inductors that present high loading reactance at the output frequency. coilcraft 0302cs series inductors were selected due to their very high self-resonant frequency and q. a 1:1 balun was ac-coupled to the output to convert the differential output to a single-ended signal and present the output with a 50- ac loading impedance. the performance of the circuit is shown in figure 52 . the average acpr of the adjacent and alternate channels is presented vs. output power. the circuit provides a 65 dbc acpr at ?13 dbm output power. the optimum acpr power level can be shifted to the right or left by adjusting the output loading and the loss of the input match. ? 60 ?70 ?25 0 05352-053 output power (dbm) acpr (dbc) ?62 ?64 ?66 ?68 ?20 ?15 ?10 ?5 adjacent channels alternate channels figure 52. single carrier w-cdma acpr performance of tx up-conversion circuit (test model 1_64)
ad8342 rev. b | page 19 of 24 the available frequency range of the ad8342 is extremely broad. with adequate care, any of the mixer ports can be optimized for extremely low frequencies, or up to several ghz. the standard evaluation board is populated for broadband performance from a few mhz to ~1ghz. the input match of the rf port degrades at higher frequencies when using the standard eval board. the broadband frequency range can be extended by minimizing parasitics between the input terminating resistor, r5, and the input pins. 8 7 6 13 15 16 comm ifop ifom 5 comm 14 2 1 3 4 comm rfcm rfin vpmx vpdc pwdn exrb comm 11 12 10 9 vplo locm loin comm ad8342 vpos 1000pf 1000pf 0.1f vpos 1nf 1nf lo in 1.82k ? 100pf rf in 1nf 100 ? vpos 1000pf 0.1f 1nf 0.1f 100pf if out (190mhz) tc2-1t 0.1f notes 1. input termination placed as close as possible to rfin and rfcm inputs. 05352-060 figure 53. modified evaluation board schematic for broadband down-conversion performance up to 3 ghz the measurements in figure 54 were made using the modified evaluation board as configured in figure 53 . 30 0 500 3000 nf, gain, oip3, ip1db (db, dbm) rf frequency (mhz) 05352-061 25 20 15 10 5 1000 1500 2000 2500 nf gain oip3 ip1db figure 54. input oip3, ip1db, gain and nf vs. rf frequency for a 190 mhz if using a low-side lo. the broadband frequency capabilities of the ad8342 makes it an attractive solution for a variety of applications, including cellular, catv, point-to-point radio links, and test equipment. as an example, the circuit depicted in figure 53 can easily be applied as a feedback mixer in a predistortion receiver design. the performance depicted in figure 55 was measured using a 160 mhz if. here, four w-cdma carriers with high par are down-converted for if sampling so that transmit path nonlinearities can be measured and minimized using digital predistortion techniques. ?30 center 160mhz span 40.6mhz ?50 ?40 ?70 ?60 ?90 ?80 ?110 ?100 ?120 4.06mhz pos ?22.564dbm ref ?22.6dbm at t 5db rbw 30khz vbw 300khz swt 4s standard: w-cdma 3gpp fwd tx channels ch1 (ref) ?20.65dbm ch2 ?20.29dbm ch3 ?20.25dbm ch4 ?20.29dbm total ?14.35dbm adjacent channe l lower ?61.36db upper ?60.84db alternate channel lower ?61.94db upper ?61.72db 05352-062 figure 55. acpr performance for multiple w-cdma carriers being down- converted from 2140 mhz to 160 mhz for distortion analysis low frequency applications the ad8342 can be used in extremely low frequency appli- cations. figure 56 depicts the configuration with necessary modifications at if ports. two 10 resistors are used to bias the open collector outputs, and the output coupling capacitors need to be large enough to allow intended low frequency operation. figure 57 illustrates the gain performance at fixed if of 10 khz and 1 mhz for broadband down-conversion using low-side lo.
ad8342 rev. b | page 20 of 24 13 12 11 10 9 1 2 3 4 14 15 16 8 7 6 5 comm 1nf 1nf 1nf lo in 0.1f 1n4148 +5 v +5v +5v 100pf 100pf 1.82k ? 0.1f 100pf 0.1f 100pf 1nf rf in 100 ? 10? 10? 10f 10f vpdc pwdn exrb comm vplo locm loin comm rfcm ad8342 rfin vpmx comm ifop ifom balanced output comm 05352-101 0 5 10 15 20 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 conversion gain (db) rf frequency (ghz) if = 1mhz if = 10khz 05352-102 figure 57. gain performance for 1 mhz and 10 khz if of broadband down- conversion figure 56. modified evaluation bo ard schematic for down-converting broadband rf to low if frequencies.
ad8342 rev. b | page 21 of 24 evaluation board an evaluation board is available for the ad8342. the evaluation bo ard is configured for single-ended signaling at the if output port via a balun transformer. the schematic for the evaluation board is presented in figure 58 . the representations of the board layout are included in figure 59 through figure 62 . r2 0 ? r1 0 ? c6 1000pf c4 1000pf c1 1000pf c3 1000pf c5 0.1f c2 0.1f vpos rf_in c7 1000pf inlo c8 1000pf c9 0.1f c10 100pf vpos r11 0 ? r16 0 ? r10 0 ? r12 open z4 open r4 open 34 16 2 tc2-1t z2 open r3 open 100? traces, no ground plane if_out+ if_out? r15 0 ? t1 z1 open z3 open r5 100 ? c14 open l1 0 ? comm ifop ifom comm comm rfcm rfin vpmx vpdc pwdn exrb comm vplo locm loin comm dut 12 11 10 9 13 14 15 16 1 2 3 4 8 7 6 5 r6 1.82k ? c11 100pf r7 0 ? c13 100pf c12 0.1f vpos gnd pwdn vpos w1 r8 10k ? r9 0 ? pwdn 05352-003 50 ? trace figure 58. evaluation board table 7. evaluation board configuration options component description default conditions r1, r2, r7, c2, c4, c5, c6, c9, c10, c12, c13 supply decoupling. shorts or power supply decoupling resistors and filter capacitors. r1, r2, r7 = 0 c4, c6 = 1000 pf c10, c13 = 100 pf c2, c5, c9, c12 = 0.1 f r3, r4 options for single-ended if output circuit. r3, r4 = open r6, c11 r bias resistor that sets the bias current for the mixer core. the capacitor provides ac bypass for r6. r6 = 1.82 k c11 = 100 pf r8 pull down for the pwdn pin. r8 = 10 k r9 link to pwdn pin. r9 = 0 c3, r5, c14, l1 rf input. c3 provides dc block for rf input. r5 provides a resistive input termination. c16 and l1 are provided for reactive matching of the input. c3 = 1000 pf r5 = 100 c14 = open l1 = 0 c1 rf common ac coupling. provides dc block for rf input common connection. c1 = 1000 pf c8 lo input ac coupling. provides dc block for the lo input. c8 = 1000 pf c7 lo common ac coupling. provides dc block for lo input common connection. c7 = 1000 pf w1 power down. the part is on when the pwdn is connected to ground via a 10 k resistor. the part is disabled when pwdn is connected to the positive supply (v s ) via w1. t1, r10, r11, r12, r15, r16, z3, z4, z1, z2, if output interface. t1 converts a diff erential high impedance if output to single-ended. when loaded with 50 , this balun presents a 100 load to the mixers collectors. the center tap of the primary is used to supply the bias voltage (v s ) to the if output pins. t1 = tc2-1t, 2:1 (mini-circuits?) r12 = open r10, r11, r15, r16 = 0 z3, z4 = open z1, z2 = open
ad8342 rev. b | page 22 of 24 05352-104 figure 59. evaluation board artwork top 05352-105 figure 60. evaluation board artwork internal 1
ad8342 rev. b | page 23 of 24 05352-106 figure 61. evaluation board artwork internal 2 05352-107 figure 62. evaluation board artwork bottom
ad8342 rev. b | page 24 of 24 outline dimensions * compliant to jedec standards mo-220-veed-2 except for exposed pad dimension. 1 0.50 bsc 0.60 max p i n 1 i n d i c a t o r 1.50 ref 0.50 0.40 0.30 0.25 min 0.45 2.75 bsc sq top view 12 max 0.80 max 0.65 typ seating plane pin 1 indicator 0.90 0.85 0.80 0.30 0.23 0.18 0.05 max 0.02 nom 0.20 ref 3.00 bsc sq * 1.65 1.50 sq 1.35 16 5 13 8 9 12 4 exposed pad bottom view 071708-a for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 63. 16-lead lead frame chip scale package [lfcsp_vq] 3 mm x 3 mm body, very thin quad (cp-16-3) dimensions in millimeters ordering guide model temperature range package description package option branding ordering quantity ad8342acpz-reel7 1 ?40c to +85c 16-lead lead frame chip scale package [lfcsp_vq], reel cp-16-3 q01 1,500 AD8342ACPZ-R2 1 ?40c to +85c 16-lead lead frame chip scale package [lfcsp_vq], reel cp-16-3 q01 250 ad8342acpz-wp 1 ?40c to +85c 16-lead lead frame chip scale package [lfcsp_vq], waffle pack cp-16-3 q01 50 ad8342-evalz 1 evaluation board 1 1 z = rohs compliant part. ?2007C2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d05352-0-7/09(b)

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